1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a hierarchical bit line structure.
2. Description of the Background Art
In large-capacity semiconductor memory devices, bit lines are hierarchically arranged in order to prevent the level of the bit line from being reduced due to a cut-off leakage current. For example, Japanese Patent Laid-Open Publication No. 6-176592 (p. 2, FIG. 2) discloses a masked ROM which stores data, depending on the presence or absence of contact connection, as an example of the semiconductor memory device having a hierarchical bit line structure.
FIG. 23 is a block diagram illustrating a structure of a conventional semiconductor memory device described in the above-mentioned document. The semiconductor memory device 90 of FIG. 23 comprises a memory cell array 91 including (n×m) subarrays 92 (MSA11 to MSAnm). The subarrays 92 are connected to n row block select lines RB1 to RBn, (n×p) word lines WL11 to WLnp, and m main bit lines MBL1 to MBLm. The subarrays 92 placed on an i-th row are connected to the row block select line RBi and the word lines WLi1 to WLip, while the subarrays 92 placed on an j-th column are connected to the main bit line MBLj.
A row decoder 8 selects one signal line from the row block select lines RB1 to RBn and one signal line from the word lines WL11 to WLnp based on an row address RA output from an input buffer 1. A column decoder 3 selects one signal line from the main bit lines MBL1 to MBLm based on a column address CA output from the input buffer 1. A sense amplifier 4 amplifies a signal on a selected main bit line. A data output buffer 5 outputs a signal amplified by the sense amplifier 4 to the outside of the semiconductor memory device 90. A precharge circuit 6 charges a selected main bit line. A leakage current compensation circuit 7 supplies electric charge to a selected main bit line in an amount corresponding to a leakage current.
FIG. 24 is a diagram illustrating a structure of the subarray 92 which is placed on the i-th row and the j-th column in the memory cell array 91. The subarray 92 includes a sub-bit line SBL, p memory cells MC1 to MCp, and a transfer gate TG. The memory cells MC1 to MCp and the transfer gate TG are each composed of an N-channel MOS transistor. All of the subarrays 92 in the memory cell array 91 have the same structure as that of FIG. 24.
The transfer gate TG is provided between the main bit line MBLj and the sub-bit line SBL. The row block select line RBi is connected to the gate electrode of the transfer gate TG. The word lines WLi1 to WLip are connected to the gate electrodes of the memory cells MC1 to MCp, respectively. A ground voltage Vss is applied to the source electrodes of the memory cells MC1 to MCp. The drain electrodes of the memory cells MC1 to MCp are connected to the sub-bit line SBL via contact elements (not shown) when data “0” is stored, and are not connected thereto when data “1” is stored. In the example of FIG. 24, the memory cell MC1 stores data 0, while the memory cell MCp stores data 1.
FIG. 25 is a diagram illustrating waveforms during an operation of the semiconductor memory device 90. An operation when data 0 is read from the memory cell MC1 (hereinafter referred to as MCA) in the subarray MSA11 (time intervals T92 to T94), and data 1 is read from the memory cell MCp (hereinafter referred to as MCB) in the subarray MSA11 (time intervals T96 to T98), will be described with reference to FIG. 25.
(1) Time Intervals T91, T95, and T99: Initial State
The row address RA and the column address CA are both in the inactive state. Therefore, all signal lines (the row block select line RB1, the word lines WL11 to WLlp, and the main bit line MBL1) connected to the subarray MSA11 have a voltage of an L level. Therefore, the transfer gate TG and the memory cells MC1 to MCp are in the OFF state, so that the sub-bit line SBL is not connected to any power source lines, and therefore, is in a floating state (high-impedance state). Note that the sub-bit line SBL is not connected to the gate electrode of any MOS transistors, and therefore, even when the sub-bit line SBL is in the high-impedance state, no malfunctions, such as an unstable operation of the transistor, and the like, occur.
(2) Time Intervals T92 and T96: Selection of Main Bit Line
When the column address CA is activated, the main bit line MBL1 is selected, and electric charge is supplied from the precharge circuit 6 to the main bit line MBL1. Since the transfer gate TG is in the OFF state, the main bit line MBL1 is charged to an H level.
(3) Time Intervals T93 and T97: Selection of Row Block Select Line
When the row address RA is activated, the voltage of the row block select line RB1 transitions to the H level. Therefore, the transfer gate TG goes into the ON state, so that the sub-bit line SBL is connected via the transfer gate TG to the main bit line MBL1. Therefore, the sub-bit line SBL is charged to the H level (more exactly, a level obtained by subtracting the threshold voltage of the transfer gate TG from a power source voltage Vdd) via the main bit line MBL1 and the transfer gate TG.
(4) Time Interval T94: Selection of Word Line (when Reading Data 0)
After a predetermined time (specifically, a sufficient time required for the voltage of the sub-bit line SBL to transition to the H level) has elapsed since the row block select line RB1 was selected, the voltage of the word line WL11 transitions to the H level, so that the memory cell MCA transitions to the ON state. The drain electrode of the memory cell MCA storing data 0 is connected via a contact element (not shown) to the sub-bit line SBL. Therefore, the sub-bit line SBL is connected via the memory cell MCA to the ground voltage Vss, so that electric charge supplied from the precharge circuit 6 in the time interval T93 flows via the main bit line MBL1, the transfer gate TG, the sub-bit line SBL, and the memory cell MCA to the ground voltage Vss. Therefore, the voltages of the main bit line MBL1 and the sub-bit line SBL transition to the L level, and an output signal of the sense amplifier 4 connected via the column decoder 3 to the main bit line MBL1 also transitions to the L level. Therefore, data 0 stored in the memory cell MCA can be read via the data output buffer 5 to the outside of the semiconductor memory device 90.
(5) Time Interval T98: Selection of Word Line (when Reading Data 1)
After the predetermined time has elapsed since the row block select line RB1 was selected, the voltage of the word line WLlp transitions to the H level, so that the memory cell MCB transitions to the ON state. The drain electrode of the memory cell MCB storing data 1 is not connected via a contact element to the sub-bit line SBL. Therefore, even after the memory cell MCB transitions to the ON state, the sub-bit line SBL is not connected to the ground voltage Vss, so that electric charge supplied from the precharge circuit 6 during the time interval T97 are still accumulated in wire capacitance possessed by the main bit line MBL1 and the sub-bit line SBL. Therefore, the voltages of the main bit line MBL1 and the sub-bit line SBL are held at the H level, and the output signal of the sense amplifier 4 connected via the column decoder 3 to the main bit line MBL1 is also held at the H level. Therefore, data 1 stored in the memory cell MCB can be read via the data output buffer 5 to the outside of the semiconductor memory device 90.
(6) At Ends of Time Intervals T94 and T98: Completion of Reading
Both of the row address RA and the column address CA return to the inactive state in order to be ready for the next read operation. Therefore, the voltages of the row block select line RB1 and the main bit line MBL1 transition to the L level. At the end of the time interval T94, the voltage of the word line WL11 transitions to the L level, and at the end of the time interval T98, the voltage of the word line WLlp transitions to the L level.
In general, in a memory cell whose drain electrode is connected via a contact element to a bit line, when a word line connected to the gate electrode thereof is in the non-selected state, a leakage current (cut-off leakage current) flows through this memory cell. Therefore, in a semiconductor memory device in which all memory cells provided on the same column are connected to a single bit line, a cut-off leakage current disadvantageously reduces the voltage of the bit line. By contrast, in a semiconductor memory device having a hierarchical bit line structure (e.g., the semiconductor memory device 90 of FIG. 23), memory cells provided on the same column are divided into subarray units, and are connected to sub-bit lines provided in corresponding subarrays. Thereby, it is possible to prevent the cut-off leakage current from reducing the voltage of the bit line. Therefore, even when finer patterning is achieved and the number of memory cells arranged in a column direction becomes so large that a significant cut-off leakage current occurs, a large-scale memory cell array can be achieved by arranging bit lines hierarchically.
However, in a semiconductor memory device in which a MOS transistor is inserted between a main bit line and a sub-bit line, and a row block select line is connected to the gate electrode of the MOS transistor, the following problem arises. For example, in the subarray 92 of FIG. 24, the sub-bit line SBL is precharged via the transfer gate TG after the main bit line MBLj is charged using the precharge circuit 6. In this case, since the transfer gate TG has ON-resistance, a time required for precharging of the sub-bit line SBL is long. Generally, in semiconductor memory devices, a word line is selected after a predetermined time (a sufficient time for a stable read operation) has elapsed since completion of precharging of a bit line. Therefore, if the precharge time of a sub-bit line increases, an access time of the semiconductor memory device increases.
An influence of the transfer gate ON-resistance becomes significant as an operating voltage decreases. For example, in the semiconductor memory device 90 of FIG. 23, when data 0 is read from the memory cell MCA, a steady-state current flows through a path to the ground voltage Vss via the main bit line MBL1, the transfer gate TG, the sub-bit line SBL, and the memory cell MCA. In this case, the transfer gate TG has a gate-source voltage Vgs which is substantially equal to the sum of a threshold voltage Vth of the memory cell MCA and a voltage drop due to the sub-bit line SBL. On the other hand, since the transfer gate TG has a connection form as a source follower, the threshold voltage Vth of the transfer gate TG is higher than that of a typical N-channel MOS transistor due to the substrate bias effect. In this case, if the gate voltage of the transfer gate TG decreases with a decrease in the operating voltage, the gate-source voltage Vgs of the transfer gate TG decreases. If the operating voltage further decreases, the gate-source voltage Vgs, in an extreme case, becomes the threshold voltage Vth or less, so that the transfer gate TG may be cut off (in other words, the ON-resistance of the transfer gate TG becomes extremely high). Thus, the presence of the transfer gate TG is responsible not only for an increase in the access time, but also for hindrance of achievement of a low voltage.
The above-described problem is significant for high-speed and low-power-consumption semiconductor memory devices which are used in mobile information apparatuses or the like. Therefore, in recent years, a method of canceling a reduction in threshold voltage by increasing the gate voltages of a portion of N-channel MOS transistors, and a method of reducing the threshold voltage of a specific N-channel MOS transistor into a lower level than those of the other N-channel MOS transistors, have been proposed. However, in the former method, a large-scale power source circuit is required, so that the chip area and the circuit cost increase. In the latter method, a specialized step for reducing the threshold voltage of a specific N-channel MOS transistor is required, so that the circuit cost increases.